Commit Graph

5 Commits

Author SHA1 Message Date
ae44d43175 implementing op codes 2025-05-02 10:46:49 +01:00
a3e3fbaa6e implementing op codes 2025-04-30 11:15:02 +01:00
611bfe0f74 implementing op codes 2025-04-30 11:14:27 +01:00
f351704b6e implementing op codes 2025-04-28 14:40:54 +01:00
e6113316bf Implement basic CPU architecture with instruction set
This commit sets up a foundational CPU simulation with registers, a memory bus, and an initial instruction set implementation in Rust. It includes operations like ADD, SUB, AND, and bit manipulations, as well as basic project configurations through Cargo and IDE settings.
2025-04-26 08:40:42 +01:00