Commit Graph

14 Commits

Author SHA1 Message Date
5848bdcdce Refactor and improve instruction execution behavior
Standardize instruction cycle handling and update return types for better clarity and accuracy. Add cycle count assertions in tests to ensure proper execution timings. Minor formatting fixes and typo corrections throughout the codebase.
2025-05-15 17:22:46 +01:00
cc0278508e Refactor CPU execution flow and improve program counter handling
Introduced `ExecutionReturn` struct to standardize program counter and cycle updates across instructions. Removed redundant handling of program counter increments and refactored control flow for clarity. Also removed unused `Address` target variant from `Target` enum.
2025-05-15 16:43:42 +01:00
03c3c8a4ac Add LCDControlRegister for LCD control bit manipulation
Introduce a new `LCDControlRegister` struct to manage and manipulate individual bits of the LCD control register. Implement `From<u8>` and `Into<u8>` conversions for seamless integration with byte-level operations. This enhances code clarity and simplifies bitwise operations related to LCD control.
2025-05-14 16:33:35 +01:00
b8c49682e2 Refactor instruction parsing logic into separate module
The implementation of instruction parsing has been moved out of `main.rs` into a dedicated `instructions` module. This improves code readability, reduces clutter, and promotes modularity, making it easier to maintain and extend the instruction set functionality.
2025-05-14 16:08:50 +01:00
11f0bb06d6 Refactor CPU instruction set and cleanup unused code
Removed unused instructions (CopyHN16A, CopyHCA, etc.), simplified PC increment logic, and cleaned up test and execution code. Updated dictionaries and Cargo.lock to reflect recent changes in project structure and dependencies.
2025-05-14 08:59:12 +01:00
e9a40bd9f7 Refactor and extend CPU and memory emulation.
Added and refactored several instructions and memory operations, improving accuracy and functionality for emulation. Introduced new dependencies (`serde_json`, `glob`) and submodule for test framework integration. Enhanced debugging, flat RAM handling, and opcode parsing while fixing multiple calculation and flag-setting issues.
2025-05-09 13:47:26 +01:00
9be93f4aa9 Refactor boot process and instruction execution
Introduce clearer boot ROM handling and streamline `execute_next_instruction` for better readability and accuracy. Add program counter (`pc`) updates within each instruction, improving program flow consistency.
2025-05-06 16:20:23 +01:00
74e86f1ab7 Add GameRom struct with MBC1 support and integrate with MemoryBus
Introduced `GameRom` struct and implemented support for MBC1 cartridges, including ROM and RAM banking. Modified `MemoryBus` and `CPU` to use `GameRom` for cartridge interactions, replacing raw game ROM handling. Added logic to load, read, and write cartridge memory based on type and address.
2025-05-06 12:00:52 +01:00
918c9020b5 Add system-specific boot symbols and CPU instruction tests
Introduced symbol files for various Game Boy systems (CGB, AGB, MGB, SGB) to define boot sequences and functionalities. Included CPU instruction behavior tests, with detailed coverage of standard operations and interrupt handling. Added documentation for test execution and internal framework operations.
2025-05-02 17:33:07 +01:00
ae44d43175 implementing op codes 2025-05-02 10:46:49 +01:00
a3e3fbaa6e implementing op codes 2025-04-30 11:15:02 +01:00
611bfe0f74 implementing op codes 2025-04-30 11:14:27 +01:00
f351704b6e implementing op codes 2025-04-28 14:40:54 +01:00
e6113316bf Implement basic CPU architecture with instruction set
This commit sets up a foundational CPU simulation with registers, a memory bus, and an initial instruction set implementation in Rust. It includes operations like ADD, SUB, AND, and bit manipulations, as well as basic project configurations through Cargo and IDE settings.
2025-04-26 08:40:42 +01:00