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Implement basic CPU architecture with instruction set

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This commit sets up a foundational CPU simulation with registers, a memory bus, and an initial instruction set implementation in Rust. It includes operations like ADD, SUB, AND, and bit manipulations, as well as basic project configurations through Cargo and IDE settings.
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Ajurna
2025-04-26 08:40:42 +01:00
commit e6113316bf
11 changed files with 453 additions and 0 deletions
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# Default ignored files
/shelf/
/workspace.xml
# Editor-based HTTP Client requests
/httpRequests/
# Datasource local storage ignored files
/dataSources/
/dataSources.local.xml