Ajurna
e6113316bf
This commit sets up a foundational CPU simulation with registers, a memory bus, and an initial instruction set implementation in Rust. It includes operations like ADD, SUB, AND, and bit manipulations, as well as basic project configurations through Cargo and IDE settings.
6 lines
180 B
XML
6 lines
180 B
XML
<?xml version="1.0" encoding="UTF-8"?>
|
|
<project version="4">
|
|
<component name="VcsDirectoryMappings">
|
|
<mapping directory="$PROJECT_DIR$" vcs="Git" />
|
|
</component>
|
|
</project> |