Ajurna
e6113316bf
This commit sets up a foundational CPU simulation with registers, a memory bus, and an initial instruction set implementation in Rust. It includes operations like ADD, SUB, AND, and bit manipulations, as well as basic project configurations through Cargo and IDE settings.
9 lines
176 B
Plaintext
9 lines
176 B
Plaintext
# Default ignored files
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/shelf/
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/workspace.xml
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# Editor-based HTTP Client requests
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/httpRequests/
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# Datasource local storage ignored files
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/dataSources/
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/dataSources.local.xml
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