implementing op codes

src/instructions.rs

@@ -14,6 +14,10 @@ impl MemoryBus {
     fn read_byte(&self, address: u16) -> u8 {
         self.memory[address as usize]
     }
+    fn write_byte(&mut self, address: u16, value: u8) {
+        self.memory[address as usize] = value;
+    }
+
 }
 
 enum Target {
@@ -27,7 +31,10 @@ enum Instruction {
     ADC(Target),
     ADD(Target),
     ADDHL(TargetU16Register),
+    ADDSP(u8),
     AND(Target),
+    BIT(u8, Target),
+    CALL(u16),
     
     SUB(TargetRegister),
     SBC(TargetRegister),
@@ -43,7 +50,7 @@ enum Instruction {
     RLA,
     RRCA,
     CPL,
-    BIT(u8, TargetRegister),
+    
 }
 enum TargetRegister { A, B, C, D, E, H, L, }
 enum TargetU16Register {AF, BC, DE, HL, SP, PC}
@@ -73,7 +80,10 @@ impl CPU {
     fn get_target_value(&mut self, target: Target) -> u8 {
         match target {
             Target::U8Register(target_register) => { self.get_u8_reg_value(target_register) },
-            Target::U16Register(target_register) => { self.bus.read_byte(self.get_u16_reg_value(target_register)) },
+            Target::U16Register(target_register) => { 
+                let address = self.get_u16_reg_value(target_register);
+                self.bus.read_byte(address) 
+            },
             Target::Address(address) => { self.bus.read_byte(address) },
         }
     }
@@ -109,7 +119,15 @@ impl CPU {
                 self.registers.f.carry = did_overflow;
                 self.registers.f.half_carry = (new_value & 0xFF) + (value & 0xFF) > 0xFF;
             }
-            
+            Instruction::ADDSP(value) => {
+                let offset = (value as i16) as u16;
+                let (new_value, did_overflow) = self.sp.overflowing_add(offset);
+                self.sp = new_value;
+                self.registers.f.zero = false;
+                self.registers.f.subtract = false;
+                self.registers.f.carry = did_overflow;
+                self.registers.f.half_carry = (new_value & 0xFF) + (offset & 0xFF) > 0xFF;
+            }
             Instruction::AND(target) => {
                 let value = self.get_target_value(target);
                 self.registers.a = value & self.registers.a;
@@ -118,8 +136,28 @@ impl CPU {
                 self.registers.f.carry = false;
                 self.registers.f.half_carry = true;
             }
+            Instruction::BIT(bit, target) => {
+                let value = self.get_target_value(target);
+                self.registers.f.zero = value >> bit & 0x1 == 0;
+                self.registers.f.subtract = false;
+                self.registers.f.half_carry = true;
+            }
+            Instruction::CALL(address) => {
+                // Decrement stack pointer
+                self.sp = self.sp.wrapping_sub(2);
+                
+                let pc = self.pc;
+                self.bus.write_byte(self.sp + 1, ((pc >> 8) & 0xFF) as u8);
+                self.bus.write_byte(self.sp, (pc & 0xFF) as u8);
+
+                // Jump to the target address
+                self.pc = address;
+            }
+
+
+
+
 
-            
             Instruction::SUB(target) => {
                 let value = self.get_u8_reg_value(target);
                 let (new_value, did_overflow) = self.registers.a.overflowing_sub(value);
@@ -296,12 +334,7 @@ impl CPU {
                 self.registers.f.subtract = true;
                 self.registers.f.half_carry = true;
             }
-            Instruction::BIT(bit, target) => {
-                let value = self.get_u8_reg_value(target);
-                self.registers.f.zero = value >> bit & 0x1 == 0;
-                self.registers.f.subtract = false;
-                self.registers.f.half_carry = true;
-            }
+
             
         }
     }